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- Path: w350zrz.zrz.TU-Berlin.DE!rawneiha
- From: rawneiha@w350zrz.zrz.TU-Berlin.DE (Philipp Boerker)
- Newsgroups: comp.sys.amiga.programmer
- Subject: Re: Processors
- Date: 25 Mar 1996 10:14:27 GMT
- Organization: Technical University Berlin, Germany
- Message-ID: <4j5rm3$cq9@brachio.zrz.TU-Berlin.DE>
- References: <4iri6d$lim@columba.udac.uu.se> <1665.6656T1237T1226@teclink.net>
- NNTP-Posting-Host: w350zrz.zrz.tu-berlin.de
-
- rad@teclink.net (rad) writes:
-
- >On 21-Mar-96 12:31:09, Kristofer Maad <m93kma@sabik.tdb.uu.se> wrote:
- >>travis (envision@darwin.topend.com.au) wrote:
- >>: You must remember that Motorola considers the processor speed to be the bus
- >>: speed. The 040 actually runs at twice the bus speed.
-
- >>No, it doesn't. This has been said a thousand times on this and other
- >>newsgroups: The '040 uses a double internal clock _only_ for pipeline
- >>synchronization purposes. No instructions are performed in an odd
- >>number of 80MHz-cycles. The fastest instruction takes one
- >>40MHz-cycle. On the 486, though, the processor is _really_ clock
- >>doubled, so some instructions take only one 66MHz-cycle to complete.
-
- >Ummm, you're only half right. The integer unit runs at the rated speed;
- >however, the FPU is run at the higher clock rate. Check out the 68040 user's
- >manual and you should see that several FPU instructions take fractional
- >numbers of cycles in the Execution stage... (FDIV 37.5, FMOVE, 1.5 or 4.5
- >FABS, FNEG 4.5) It has been confirmed by Motorola Engineers on
- >comp.sys.m68k that the FPU is based on the "double" clock.
-
- No, there is no double clock, there is only a clock, that is delayed half a cycle.
- The fractional cycle is only a timing problem that needs the second clock
- for handling!
- Believe me!
-
- Greets,
- Phil.
-